1. Field of the Invention
This invention relates to a method of designing an LSI logic circuit using a CAD (Computer Aided Design) used to determine a layout such as the placement of interconnections and circuit elements used for LSI design, particularly laying out interconnections employed in the LSI logic circuit.
2. Description of the Related Art
Various problems arise upon design of an LSI logic circuit using a CAD system, which comprises various logic elements such as flip-flops, inverters, etc. For example, each element logic elements to be activated in synchronism with a clock signal must be set so that the clock signal is transferred thereto without a clock skew developed due to variations in signal delay (or within an allowable range). In this case, wiring capacitance of each clock interconnection used to transfer a clock signal inputted to the LSI logic circuit from the outside to each logic element activated in synchronism with the clock signal, and a clock skew developed due to a wiring resistance thereof present a problem in particular.
Therefore, various methods for laying out interconnections have heretofore been used. FIGS. 18 through 21 respectively show wiring layout methods which have heretofore been used. Incidentally, FIGS. 18 through 21 are shown as LSI logic circuits each composed of an gate array LSI.
FIGS. 18 and 19 respectively illustrate a wiring layout method called "trunk system". In FIGS. 18 and 19, an interconnection (hereinafter called "trunk") 4 dedicated to a clock signal is laid out substantially in the center of a core region (where a logic circuit is configured) 2 surrounded by an input/output element region 3 located around an LSI chip for an LSI logic circuit 1. In FIG. 18, the clock signal inputted from the outside is transferred to the trunk 4 through a drive element (hereinafter called "driver") 5-1 or 5-2 formed within the input/output element region 3. If the clock signal is transferred to the main trunk 4 from both the drivers 5-1 and 5-2 in this case, then a signal delay and a clock skew can be reduced even if the clock signal is taken out or selected from any position of the trunk 4. In FIG. 19, drivers 8-1 through 8-4 are provided within a core region and a clock signal is transferred to a main trunk 4 from various positions of the main trunk 4. In the method shown in FIG. 19, a signal delay and a clock skew can be lessened by placing the drivers 8-1 through 8-4 so that they are well balanced therebetween. In doing so, the clock signal can be transferred to respective logic elements 7 through a subtrunk interconnection 6 that has branched off from the trunk 4.
FIGS. 20 and 21 respectively show wiring layout methods called "tree systems". FIG. 20 illustrates an H-type tree system. In FIG. 20, an H-type interconnection 51 is decided from a main driver 11 that receives therein a clock signal inputted from the outside. At this time, the main driver 11 is positioned substantially in the center of the H-type interconnection 51. The clock signal is transferred to respective H-type interconnections 52 through 55 through drivers 12-1 through 12-4 provided at leading ends of the interconnection 51. Thus, respective logic elements to be disposed at leading ends of the H-type interconnections 52 through 55 and the main driver 11 can be rendered identical in both wiring length and number of driver's stages to one another. Referring to FIG. 21, the next drivers 14-1 through 14-4 are disposed substantially in the centers of the respective sides forming a rhombus with a main driver 13 as the center, as viewed from the main driver 13. The main driver 13 and the respective drivers 14-1 through 14-4 are respectively electrically connected to each other by an interconnection 61. If necessary, for example, a rhombus is formed with the driver 14-4 as the center and the same processing as described above is executed. Thereafter, the driver 14-4 and the next drivers 15-1 through 15-3 are respectively electrically connected to each other by an interconnection 62. Since the wiring lengths and the numbers of driver's stages between the main driver 11 or 13 and the respective logic elements can be uniformly set by doing so, a signal delay and a clock skew can be reduced.
However, the above-described methods have the following problems respectively. FIGS. 22 and 23 are views for explaining the problems.
There may be cases in which, for example, configurations 20-1 and 20-2 called "macrocells" are disposed within a core region 2 in FIG. 22. Each of the macrocells is a circuit configuration designed in advance and registered in a computer and is one such as a memory or a CPU. Since the large macrocells 20-1 and 20-2 are laid out, they occupy the core region extensively in FIG. 22. Therefore, the trunk 4 cannot be set and the region for constructing the tree results in a shape deformed in L form as shown in FIG. 22, e.g., trapezoidal form. Thus, substantial limitations are imposed on the wiring layout.
Referring to FIG. 23, a small region 21 is defined between a macrocell 20-3 and an input/output element region 3 when the macrocell 20-3 must be laid out away from the input/output element region 3. When logic elements to receive a clock signal in synchronism with other logic elements must be laid out within the region 21, it becomes eventually necessary to provide interconnections that bypass the macrocell 20-3 even if the trunk and tree systems are used.
With the foregoing problems in view, it is therefore an object of the present invention to allow respective logic elements activated in synchronism with a predetermined signal to be laid out and wired easily even if configurations like macrocells are laid out in any form and to reduce a wiring delay and a clock skew to the utmost.